1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits requiring a complex metallization system including a high number of metallization layers.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may involve up to several hundred individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield. At the same time, device dimensions are also being reduced in view of performance criteria, as typically lower transistor dimensions provide increased operating speed.
In modern integrated circuits, the circuit elements are formed in and on a semiconductor layer, while most of the electrical connections are established, due to the high packing density of the circuit elements in the device level, in a plurality of “wiring” layers, also referred to as metallization layers, wherein the electrical characteristics, such as resistivity, electromigration, etc., of the metallization layers significantly affect the overall performance of the integrated circuit. Electromigration is a phenomenon of electric field induced material transport in a metal line, which is observable at higher current densities in a metal line, thereby resulting in device degradation or even device failure.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, metals of superior conductivity, such as copper and the like, in combination with sophisticated dielectric materials, have become a frequently used alternative in the formation of metallization systems comprising metallization layers having metal line layers and intermediate via layers. Metal lines act as intra-layer connections and vias act as inter-layer connections, thereby connecting the individual circuit elements in the device layer to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other are necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements in the device levels, such as transistors, but is limited—owing to the increased density of circuit elements, which requires an even more increased number of electrical connections between these circuit elements—by the close proximity of the metal lines, since the line-to-line capacitance is increased. This fact, in combination with a reduced conductivity of the lines due to a reduced cross-sectional area, results in increased RC time constants. For this reason, traditional dielectrics such as silicon dioxide and silicon nitride are increasingly replaced in metallization layers by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics having a relative permittivity of approximately 3 or less.
Furthermore, due to the ongoing shrinkage of feature sizes of the circuit elements in the device layer, the available floor space for forming the metallization system of the semiconductor device may also have to be adapted to the increased packing density. Since, typically, many of the circuit elements formed in the device level may require two or more electrical connections, the number of mutual electrical connections may over-proportionally increase with increasing packing density in the device level, thereby typically requiring an increased number of stacked metallization layers in order to comply with the complexity of the circuit layout under consideration. For this reason, in sophisticated semiconductor devices, such as microprocessors, complex storage devices and the like, the number of stacked metallization layers may increase although sophisticated materials in the form of highly conductive metal components, such as copper and the like, in combination with dielectric materials of reduced permittivity, may increasingly be used. Consequently, as the number of stacked metallization layers may increase, and additionally in each of the metallization layers a complex composition of materials in the form of etch stop layers, interlayer dielectric materials, conductive barrier layers, cap layers and the like may be required, the entire metallization system of the semiconductor device may have a significant influence on the overall performance of the device but also may increasingly influence the overall manufacturing flow. For example, the density and mechanical stability or strength of the low-k dielectric materials may be significantly less compared to well-approved dielectrics such as silicon dioxide and silicon nitride. Moreover, due to copper's characteristics of being readily diffused in a plurality of dielectric materials, an efficient confinement of the copper material may also be guaranteed, thereby requiring conductive barrier materials, dielectric or conductive cap layers and the like, each of which may require respective material compositions and deposition techniques. For example, the substrate handling for the various process steps required for completing the complex metallization system may be significantly affected by the composition and the number of stacked metallization layers, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100, in which a metallization system 180 is formed above a substrate 101. Typically, the substrate 101 may represent a silicon substrate or an SOI substrate, which may be divided into a plurality of die regions (not shown), each of which may represent a semiconductor device in an intermediate manufacturing stage, i.e., semiconductor device prior to separating the substrate 101 into individual chips. The substrate 101 typically has formed thereon a device layer 110, which is to be understood as any appropriate semiconductor layer or layers required for forming respective circuit elements, such as transistors, capacitors, resistors and the like. For convenience, a plurality of elements 111 is illustrated, wherein it should be appreciated that a very large number of corresponding circuit elements may be provided within each die, depending on the overall complexity of the circuit configuration under consideration. For instance, in sophisticated microprocessors, several hundred million transistors may be provided. Furthermore, a contact structure 120 is typically provided to act as an electric interface between the device level 110 and the metallization system 180. For instance, the contact structure 120 may be comprised of any appropriate dielectric material for enclosing and passivating the circuit elements 111 and also accommodating corresponding contact elements, which may connect to metal lines of the contact structure layer 120 of the metallization system 180. Moreover, as previously indicated, a plurality of additional metallization layers 130, 140, 150, 160 and 170 may be provided depending on the circuit layout of the device 100. In principle, each of the metallization layers 120, 130, 140, 150, 160 may have a similar composition, i.e., metal lines and vias may be formed in accordance with the overall circuit layout in an appropriate dielectric material, wherein respective additional materials, such as etch stop materials, conductive and dielectric barrier materials and the like, are typically provided as required. Moreover, as schematically illustrated in FIG. 1a, a last metallization layer 170 may typically be provided if an appropriate structure is provided to connect the metallization system 180 to the periphery, for instance in the form of a printed wiring board, a device package, or any other carrier substrate in accordance with the further handling of the device 100. For example, a bump structure 171 may be provided to enable direct contact with corresponding bumps or contact pads of a carrier substrate. In other cases, appropriate bond pads may be provided in order to enable contact with a bond wire, which may be used for establishing the electrical connection to the periphery.
FIG. 1b schematically illustrates an enlarged view of a portion of the metallization system 180. As illustrated, the portion of the metallization layer 140 comprises a dielectric material 141, which may be provided in the form of a material composition including different materials while, in sophisticated applications, the dielectric material 141 may comprise a significant amount of a low-k dielectric material or even an ultra low-k (ULK) material, which may have a dielectric constant of 2.7 and less. Furthermore, an etch stop layer 145 is typically provided as a first layer of the metallization layer 140 or may be considered as a final layer of a lower lying metallization layer and has typical etch stop capabilities with respect to the interlayer dielectric material 141 with respect to a patterning sequence for forming openings for a via 143. Moreover, a metal line 142 is illustrated wherein, in the example shown, the via 143 and the metal line 142 may both comprise a common conductive barrier material 144, such as tantalum, tantalum nitride and the like, which are well-established barrier materials for enhancing adhesion of the highly conductive metal, such as copper, provided in the metal line 142 and the via 143, while also providing the required copper integrity and performance with respect to electromigration. Similarly, the metallization layer 150 may comprise an etch stop layer 155 comprised of an appropriate dielectric material 151, in which are embedded a metal line 152 and a via 153. It should be appreciated that other materials may be used for the dielectric material 151 compared to the material 141 depending on the overall configuration of the semiconductor device 100.
As previously discussed, a plurality of complex manufacturing steps are typically required for forming the metallization system 180, wherein, for convenience, a corresponding manufacturing sequence for the layers 140 and 150 may be described. Hence, after forming the metallization layer 130 (FIG. 1a), the etch stop layer 145 is deposited, for instance in the form of a silicon nitride material, a nitrogen-containing silicon carbide material and the like. For this purpose, well-established plasma enhanced deposition techniques are available. Subsequently, the dielectric material 141 may be provided by one or more deposition steps, such as chemical vapor deposition (CVD), spin-on techniques and the like. Thereafter, a complex patterning sequence has to be performed on the basis of sophisticated lithography processes to form the corresponding openings for the via 143 and the metal line 142. It should be appreciated that a plurality of process strategies are currently practiced in order to form the metal line 142 and the via 143. Irrespective of the corresponding manufacturing flow, a plurality of critical deposition and patterning steps are to be performed, wherein the process results may increasingly be determined by the overall configuration of the metallization system 180. That is, due to the very different materials and treatments to be performed on the previously deposited material layers, a certain degree of deformation or warpage of the substrate 101 may be caused, which in turn may have a significant influence on the substrate handling during the entire processing of the device 100. For example, critical lithography processes may be severely influenced by the position of the corresponding substrate portions on a corresponding substrate holder so that the finally obtained lithography result may depend on the characteristics of the substrate 101. Moreover, an even further increased degree of deformation or warpage may result in a non-reliable attachment of the substrate 101 to the various substrate holders of process tools and transport equipment, thereby resulting in a significant risk of damage of the substrate or other related substrates.
Consequently, upon filling the corresponding openings in the dielectric material 141 by depositing the conductive barrier material 144 followed by the electrochemical deposition of the copper material and the corresponding removal of any excess material, the further processing may have to be performed on the basis of an even further increased substrate warpage, depending on the materials and the processes involved in forming the metallization layer 140. Similarly, the etch stop layer 155 may be deposited, followed by the deposition of the dielectric material 151 and the patterning thereof, wherein the previous metallization layers as well as the additional material layers 155 and 151 influence the mechanical characteristics of the substrate 101 so that a high risk of loss of substrates may be encountered during the manufacturing of the metallization system 180, which may even increase for higher metallization layers. Consequently, due to mechanical influence of the metallization system 180 on the substrate 101, a significantly reduced reliability during substrate handling activities may occur, in particular at a very late stage of the overall manufacturing flow, thereby contributing to increased yield losses at a manufacturing stage in which most of the process flows have already been completed.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.